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2014 - Silicon Valley

Designing Change

Dr. Aart de Geus, Chairman and co-CEO -Synopsys Inc.

Track - Keynote

2015 - Austin

The Rubber Jigsaw Puzzle - Floorplanning for Network-on-Chip

Jonah Probell, Byungchul Hong, Brian Huang - Arteris

Track - Backend Implementation

2014 - Silicon Valley

An Investigation of the Efficacy of PT-ADV in a Non-Synopsys PnR Flow

Jim Fong - Rambus; Po Leung - Synopsys, Inc.

Track - Characterization & Signoff

2014 - Silicon Valley

Using Lynx Design System Automation to Accelerate Design Processes - SoC Flow, Custom Design Correlation and Regression Throughput

Steve Cline - Altera Corporation; Eduardo Flores, Lydia Lee, Terry O'Brien - Synopsys, Inc.

Track - Implementation

2015 - Austin

Performance of SystemVerilog Sudoku Solver with Synopsys VCS (Best Presentation - 2nd Place)

Jeremy Ridgeway - Avago Technologies

Track - Digital Verification

2015 - Austin

Verification of a Cache Coherent System with an A53 Cluster Using ACE VIP with Graph Based Stimulus

Galen Blake, Perry Wobil - Altera Corporation

Track - Digital Verification

2015 - Austin

Is Your Testing N-wise or Unwise? Pairwise and N-wise Patterns in SystemVerilog for Efficient Test Configuration and Stimulus

Kevin Johnston, Jonathan Bromley - Verilab

Track - Digital Verification

2015 - Austin

Obtaining a Maximally Compressed Verification Test Set

James Longino, Mrinal Bose - Samsung Austin R&D Center

Track - Digital Verification

2015 - Austin

RTL-Agent Switch - Implementation and Applications

Aman Arora, Nathan Wooster, Pavan Mula, Rob Porter - NVIDIA

Track - Digital Verification

2015 - Austin

A Vendor-Independent Formal Unreachability Analysis Flow for Automated Coverage Closure

Xiushan Feng - NVIDIA; Abhishek Muchandikar, Sunil Keerthi, Praveen Tiwari - Synopsys

Track - Digital Verification