2015 - Silicon Valley
Large Scale Design STA - Hierarchical or Flat, Distributed or Single Machine: Which Way to Go for Timing Signoff?
Track - Signoff & Characterization
2017 - Silicon Valley
Enabling Data-Driven Approach to Chip Design
Track - Signoff & Characterization
2017 - Silicon Valley
SpyGlass Reset Domain Crossings
Track - Verification Continuum
2017 - Silicon Valley
Introduction to SpyGlass Lint Turbo for 3X Violation Reduction to Accelerate RTL Design Closure
Track - Verification Continuum
2017 - Silicon Valley
VCS Performance Innovations – Fine-Grained Parallelism and More!
Track - Verification Continuum
2017 - Silicon Valley
Performance for Productivity
Track - Verification Continuum
2015 - Silicon Valley
IC Compiler's Latest Release (2014.09) Delivers Significant Performance Power Area Improvements and Faster Closure on Emerging and Established Nodes
Track - Implementation
2017 - Silicon Valley
Widening the Scope and Adoption of FPGA-based Physical Prototyping at ARM
Track - Verification Continuum (FPGA & Prototyping)
2017 - Silicon Valley
Trapping the Hardest to Find Hardware Bugs in the Latest ARM Cores using FPGA-based HAPS Debug Technologies
(3rd Place - Best Presentation)
Track - Verification Continuum (FPGA & Prototyping)