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2015 - Silicon Valley

IC Compiler II Technology Tutorial

Wei-Chun Chou - Synopsys

Track - Implementation

2015 - Silicon Valley

Large Scale Design STA - Hierarchical or Flat, Distributed or Single Machine: Which Way to Go for Timing Signoff?

Robert Landy - Synopsys

Track - Signoff & Characterization

2017 - Silicon Valley

Enabling Data-Driven Approach to Chip Design

Sashi Obilisetty - Synopsys

Track - Signoff & Characterization

2017 - Silicon Valley

SpyGlass Reset Domain Crossings

Sean O’Donohue - Synopsys

Track - Verification Continuum

2017 - Silicon Valley

Introduction to SpyGlass Lint Turbo for 3X Violation Reduction to Accelerate RTL Design Closure

Aloke Das, Tanveer Singh - Synopsys

Track - Verification Continuum

2017 - Silicon Valley

VCS Performance Innovations – Fine-Grained Parallelism and More!

Kiran Maiya - Synopsys

Track - Verification Continuum

2017 - Silicon Valley

Performance for Productivity

Sourabh Goyal - Xilinx; Shylaja Sen - Synopsys

Track - Verification Continuum

2015 - Silicon Valley

IC Compiler's Latest Release (2014.09) Delivers Significant Performance Power Area Improvements and Faster Closure on Emerging and Established Nodes

Shoukyou Wang - Synopsys

Track - Implementation

2017 - Silicon Valley

Widening the Scope and Adoption of FPGA-based Physical Prototyping at ARM

Peter Fogl - ARM

Track - Verification Continuum (FPGA & Prototyping)

2017 - Silicon Valley

Trapping the Hardest to Find Hardware Bugs in the Latest ARM Cores using FPGA-based HAPS Debug Technologies (3rd Place - Best Presentation)

Peter Gibbons - ARM

Track - Verification Continuum (FPGA & Prototyping)